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Tier-1 employer and Bangalore metro increase competition, but niche mixed-signal verification skills moderate applicant density.
Highly specialized semiconductor mixed-signal verification skills limit transferability across industries.
Multiple mandatory niche skills (SV/UVM, analog modeling, Cadence tools) make filters strict.
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Own creation and execution of verification strategies and plans for large integrated Digital Mixed Signal (DMS) products.
Develop analog/mixed-signal behavioral models and chip-top verification environments using standard methodologies (SV/UVM).
Collaborate with cross-functional teams (system architects, digital/analog design, post-silicon validation) to support first pass silicon and reduce time-to-market.
B.Tech or M.Tech degree.
2+ years industry experience in analog/mixed-signal behavioral modeling and full chip verification using behavioral models and digital RTL/PA/Gates.
Good understanding of analog design concepts and mixed signal architectures including blocks like Power Management, ADCs, DACs, PLL, bandgap references, oscillators, SerDes.
Proficiency in SV/UVM verification methodologies; experience with Cadence Virtuoso, Simvision, Cadence Xcelium/Synopsys VCS simulators; scripting with Python/Perl/Shell preferred.
Experienced design verification engineer with demonstrated ability to handle complex mixed-signal block and chip-level verification.
Capable of independently defining verification strategy and developing verification environments using metric-driven SV/UVM methodologies.
Strong collaborator comfortable working in a multifunctional global team, supporting post-silicon validation and driving cross-company technical initiatives.