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Tier-1 brand plus metro location increases applicant density modestly.
Highly specialized semiconductor DFT verification skills limit cross-industry transferability.
Requires specific DFT/UVM verification skills but only minimal years, so moderate filtering.
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Own verification of advanced Memory BIST logic and other DFT circuits like JTAG, IO BIST, and ATPG.
Develop robust and scalable test plans at unit and SoC/full chip level using UVM and NVIDIA internal tools, performing pre-silicon simulation and validation.
Drive automation, flow improvements, and test coverage sign-off, collaborating with design and QA teams for delivering quality test features.
Bachelor’s or Master’s degree in EE/ECE or equivalent.
Exposure to Design-for-Test circuits and methodologies.
Experience with industry-standard verification flows: constrained random testing, UVM, coverage metrics, profiling tools (1+ years preferred).
Strong coding skills in scripting languages such as SystemVerilog, Perl, Python.
Experienced in logic design, architecture, and verification of complex semiconductor chips, especially DFT-related functions.
Proficient in verification methodologies and automation for silicon test features under a rigorous verification environment.
Able to collaborate cross-functionally with design and QA teams to enhance test coverage and product quality in a high-tech semiconductor company.