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Tier-1 brand plus senior, niche EDA+LLM specialization yields medium competition.
Deep EDA and tape-out expertise required, making background fit sensitivity high.
Explicit 10+ years semiconductor requirement and mandatory applied-LLM, customer-facing skills make filters high.
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Lead end-to-end deployment of Cadence AI/LLM-powered solutions into customer silicon design flows covering RTL to packaging.
Architect and optimize AI-driven workflows and tool integrations to automate semiconductor EDA tasks, delivering measurable productivity improvements.
Serve as senior technical advisor interfacing with customer teams to drive adoption, define KPIs, and translate feedback into product enhancements.
BS/MS/PhD in EE, ECE, CS, or related field.
10+ years semiconductor/chip design experience in front-end, physical design, methodology, or tape-out leadership.
Demonstrated applied experience using LLMs/AI tools for real engineering tasks in semiconductor design contexts.
Based in or willing to relocate to Portland, OR; able to work on-site at customer locations as needed.
Experienced chip-design practitioner with deep, hands-on knowledge of industry EDA flows and tape-out challenges.
Proven ability to embed applied AI and agentic workflows within complex semiconductor design methodologies and customer environments.
Strong customer-facing communication skills comfortable engaging multiple technical levels and leading deployment ownership from pilot to production.