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Medium — mid-level experience plus metro hiring amplify competition despite specialized DV skills.
High — specialized hardware DV and microarchitecture skills have limited cross-industry transferability.
High due to explicit 5+ years, specialized SystemVerilog/UVM, and OOO microarchitecture verification requirements.
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Own verification strategy, methodology, and execution for major out-of-order CPU core subsystems including front-end, rename, issue queues, reorder buffer, load-store unit, caches, and memory interfaces.
Architect and implement SystemVerilog/UVM testbenches with reusable environments, constrained-random and targeted stimulus focused on complex out-of-order corner cases.
Define coverage models, develop assertions, drive coverage closure and sign-off; lead debug of complex verification failures and collaborate with micro-architecture, RTL, performance, and post-silicon teams.
5+ years of experience in design verification with Bachelor's or Master's degree in Engineering.
Proven expertise in verification of out-of-order CPU cores and subsystems including front-end, issue queues, reorder buffer, LSU, caches, and memory management units.
Experience with SystemVerilog and UVM testbench architecture and methodology for complex CPU verification.
Authorized to work in India; must pass background and reference checks and comply with export control laws.
Senior-level verification engineer with deep technical ownership of complex out-of-order CPU core verification blocks.
Experienced in leading verification strategy, from detailed test planning to debug and coverage sign-off, demonstrating strong cross-functional collaboration.
Technical mentor and leader skilled in advancing verification methodologies and best practices across projects and teams.