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Tier-1 brand and metro location increase competition, but niche SV/UVM ASIC verification reduces applicant pool.
Highly specialized ASIC verification skills limit transferability across industries.
Explicit 7+ years SV/UVM ASIC verification, ATE and scripting requirements enforce strict filters.
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Create and execute SoC verification plans using SystemVerilog/UVM methodologies, including test controller and MBIST verification.
Develop and enhance verification environments with monitors and automated flows, collaborating closely with Architecture, Design, and Tester teams.
Support vectors bring-up and ATE/Tester teams during functional characterization and debugging of ASIC test vectors.
Bachelor's or Master's degree in Engineering.
Minimum 7+ years of SoC/IP verification experience with SystemVerilog/UVM.
Proficiency in scripting languages such as Python, Perl, or TCL.
Strong understanding of test controller, MBIST, DFT architecture and practical experience with ATE/functional CHAZ vector enablement and silicon debug.
Experienced in complex SoC verification leadership with expertise in constrained random testing and debugging.
Familiar with industry standard interfaces like PCIe, LPDDR, ONFI/NAND (desired but not strictly mandatory).
Capable of driving team automation efforts and integrating cross-functional ASIC verification and test requirements in an engineering environment.