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Tier-1 brand and metro location increase competition, but specialized IP verification reduces applicant pool.
Specialized IP-level verification, SystemVerilog/UVM expertise, and hardware-focused skills limit cross-industry transferability.
Explicit 8+ years requirement and mandatory SystemVerilog/UVM and testbench skills create stringent screening.
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Lead IP-level verification efforts with a focus on security-related IPs such as cryptography, PRNG, and RSA algorithms.
Develop and debug SystemVerilog/UVM based testbenches and verification environments from scratch using VCS tools.
Collaborate across teams to ensure compliance with digital design fundamentals and bus protocols (AHB, AXI, APB), and apply functional and code coverage methodologies.
8+ years of experience in IP-level verification specifically in hardware engineering context.
Proficiency in SystemVerilog and UVM, with hands-on experience in testbench architecture and development.
Strong understanding of digital design fundamentals and Verilog; experience debugging with VCS tools.
Bachelor’s degree or higher in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years (Bachelor), 3+ years (Master’s), or 2+ years (PhD) of relevant work experience.
Experienced in security IP verification with knowledge of cryptographic algorithms and related technologies.
Comfortable working on complex verification projects requiring deep technical skills in SystemVerilog, UVM, and digital design.
Familiar with standard bus protocols and coverage methodologies, potentially with exposure to formal verification tools like VC Formal or JasperGold.