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Tier-1 employer and metro Hyderabad increase applicant density, but niche hardware DV reduces it.
Highly specialized DDR design-verification skills are industry-specific and not easily transferable.
Mandatory 11+ years and specific DV/UVM/SystemVerilog expertise make filters strict.
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Develop and maintain design verification infrastructure for LPDDR/DDR IPs and subsystems within the Infra IP team.
Create and execute detailed test plans, debug verification failures, write assertions, and manage coverage closure to ensure high-quality verification.
Collaborate with stakeholders across teams to drive program success and resolve issues efficiently.
Bachelor's degree in Engineering, Electronics, Computer Science or related field; Master's or PhD with relevant experience also acceptable.
11+ years of hardware engineering or related work experience.
Strong skills in UVM, SystemVerilog, and debugging complex verification environments.
Experience with DDR/LPDDR families (including DDR2/3/4/5), bus protocols such as AHB/AXI/ACE, and digital design verification methodologies.
Experienced senior verification engineer with deep expertise in design verification infrastructure and methodologies for DDR/LPDDR IPs.
Strong analytical and debugging skills to independently investigate and resolve complex testbench failures.
Comfortable navigating large verification environments and collaborating with cross-functional teams to meet project goals.