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Tier-1 brand and Noida metro increase competition, but senior niche DV skills limit applicant density.
Highly domain-specific hardware DV skills (SystemVerilog, UVM, AMBA, NOC) limit cross-industry transferability.
Explicit senior years requirement and mandatory SystemVerilog/UVM/AMBA/NOC skills create high shortlisting strictness.
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Lead end-to-end verification strategy, planning, and execution for complex IP/SoC subsystems with a focus on Network on Chip (NOC) verification.
Architect, develop, and manage scalable UVM-based verification environments including testbench components like agents, scoreboards, monitors, sequences, and coverage models.
Drive coverage closure (functional and code), debug RTL and verification issues, mentor DV engineers, and manage multiple concurrent projects with ownership of timelines and quality.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering or related work experience; or Master's with 3+ years; or PhD with 2+ years.
Strong expertise in SystemVerilog and UVM verification methodologies.
Experience in NOC verification and AMBA protocols (AXI/AHB/APB).
Proficiency in debugging, constrained random verification, functional coverage, SystemVerilog Assertions (SVA), and scripting languages Perl and/or Python.
Experienced in leading verification teams and large-scale projects demonstrating cross-site and cross-functional collaboration.
Technical depth in verification methodology and IP/SoC level verification with strong hands-on skills in SystemVerilog UVM environments and protocol knowledge including AMBA and preference for coherency and SoC/interconnect protocols.
Capable of mentoring engineers and driving verification excellence through best practices in automation, regression optimization, and integration/reuse strategies.