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Niche VLSI verification skills reduce applicants, but Bangalore location and 3–6 year band increase competition.
VLSI verification skills are highly specialized and not easily transferable across industries.
Explicit 4–6 years DV requirement and mandatory UVM/SystemVerilog/formal skills make filters strict.
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Define and own the verification strategy including methodology, tools, and infrastructure selection primarily using UVM/SystemVerilog.
Design scalable and reusable testbench architectures including BFMs, monitors, scoreboards, and checkers, and develop complex test cases for high functional coverage.
Lead debugging of complex design issues, manage functional and code coverage metrics, oversee gate-level simulations, and provide sign-off for verification completion.
Bachelor's or Master's degree in Electronics, VLSI, or related field (B.E./B.Tech or M.Tech/M.S.).
4 to 6 years of hands-on Design Verification (DV) experience in semiconductor, ASIC, or SoC companies.
Proficiency in UVM/SystemVerilog methodologies and verification tools.
Work Experience Required: 4-6 years in relevant domain.
Strong technical leadership with experience mentoring junior engineers and leading cross-functional teams across design, architecture, and emulation.
Experienced planner capable of managing verification schedules, identifying risks, and prioritizing tasks to meet project deadlines.
Practiced in advanced verification techniques including constrained random testing and formal verification to validate complex ASIC/SoC designs.