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Tier-1 employer and Bengaluru location increase competition, but niche hardware DV skills limit applicants.
Highly domain-specific semiconductor verification skills limit cross-industry transferability.
Explicit 7–10 years DV plus mandatory SystemVerilog/UVM/formal and bus-protocol expertise makes filters highly strict.
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Define and execute the overall DV verification strategy and architecture, focusing on scalable, reusable testbench design using UVM/SystemVerilog.
Lead DV execution for small to mid-sized customer ASIC projects, including translating customer requirements into verification plans, test case development, and complex design bug debugging.
Oversee coverage analysis, formal verification, gate-level simulations, and provide final technical approval for verification sign-off.
7–10 years hands-on DV experience in semiconductor/ASIC/SoC companies.
Degree: B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field.
Deep expertise in SystemVerilog, UVM, and digital design fundamentals (RTL, timing, clocking, resets).
Experience with industry-standard simulators (Xcelium, VCS, Questa), bus protocols (AXI, AHB, APB, PCIe, DDR), formal verification tools, and power-aware simulation (UPF/CPF).
Experienced in leading verification strategy and execution with demonstrated ability to manage customer interactions and define verification plans from high-level requirements.
Strong in technical leadership including mentoring junior engineers and cross-functional collaboration with design, architecture, and emulation teams.
Operates effectively in complex ASIC/SoC environments requiring deep verification expertise and project management to meet timelines and quality goals.