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Tier-1 employer but specialized ASIC verification role reduces applicant density, yielding medium competition.
Highly domain-specific ASIC verification skills limit cross-industry transferability.
Requires SystemVerilog/UVM expertise and engineering degree, enforcing highly rigid shortlisting filters.
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Architect and develop block-level verification environments for ASIC sub-systems and full chips using SystemVerilog and UVM methodology.
Define, code, and deliver verification suites/tests for ASICs, performing coverage analysis and gate-level simulation, enabling tape-out sign-off.
Collaborate with logic designers and software developers to resolve bugs and assist in software bring-up; develop scripts (Perl, Python, shell) to improve verification infrastructure.
Strong experience with ASIC verification using SystemVerilog and verification methodologies like UVM, OVM, or VMM.
MSEE or BSEE degree is mandatory.
Experience with constrained-random verification and scripting in Perl/Tcl preferred but scripting requirement is strong.
Work location is onsite at an HPE office as explicitly mentioned.
Experienced in handling large ASIC blocks independently with strong debugging and problem-solving skills.
Skilled in using front-end simulator tools such as VCS/NC and performing detailed coverage and gate-level simulations.
Familiarity with networking protocols such as Ethernet is desirable for this role.