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Tier-1 employer, mid-level requirement, and Bangalore metro location increase competition despite niche skills.
Highly specialized ASIC verification skills with SystemVerilog/UVM limit cross-industry transferability.
Mandatory 5+ years ASIC verification, SystemVerilog/UVM, simulator and scripting skills required.
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Develop and enhance ASIC verification environments using UVM and SystemVerilog across block-level to full-chip scope.
Define, design, and execute verification suites and test cases using simulators like VCS and NC to ensure tape-out readiness including coverage analysis and gate-level simulations.
Collaborate with logic designers and software teams to debug design issues and improve verification automation via scripting languages such as Perl, Python, and Shell.
Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE).
Minimum 5 years of experience in ASIC Verification.
Strong skills in SystemVerilog and constrained-random verification with experience in methodologies such as UVM, OVM, or VMM.
Onsite work requirement at HPE office explicitly mentioned.
Experienced in large ASIC block verification with a demonstrated ability to independently drive tape-out readiness.
Proficient in scripting (Perl, Tcl, Python, Shell) to create verification infrastructure and automation, indicating a technical and automation-focused operating style.
Comfortable working closely with cross-functional teams including logic design and software during bring-up and validation phases.