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Tier-1 employer and Bangalore metro increase applicant density despite niche ASIC verification skills.
ASIC SystemVerilog and UVM skills are hardware-specialized and not easily transferable across industries.
Requires SystemVerilog/UVM ASIC verification expertise, enforcing stringent technical filtering.
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Architect and develop block-level, subsystem, and full-chip verification environments using SystemVerilog and UVM.
Define, code, and deliver verification suites and test cases for ASICs, ensuring readiness through coverage analysis and gate-level simulations.
Collaborate with design and software teams to resolve bugs and support software bring-up; develop scripts to automate verification infrastructure.
Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE).
Strong experience in ASIC verification using SystemVerilog with constrained-random techniques and UVM/OVM/VMM methodologies.
Proficiency in scripting languages such as Perl, Tcl, Python, or Shell (Perl/Tcl preferred).
Work Experience Required: Not explicitly mentioned in the JD; Role requires onsite work from HPE office.
Experienced in front-end ASIC verification with ability to independently verify large ASIC blocks and drive tape-out readiness.
Skilled in debugging and analytical problem solving within ASIC design and verification contexts.
Comfortable working collaboratively with global teams across design and software domains, and adapting verification infrastructure through automation.