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Tier-1 employer and Bangalore metro increase competition, but niche ASIC verification skills limit candidate pool.
ASIC verification skills are highly domain-specific and less transferable across industries.
Mandatory degree plus specialized SystemVerilog/UVM and verification expertise enforce strict shortlisting filters.
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Architect and develop block-level ASIC verification environments using SystemVerilog and UVM methodology.
Define, develop, and deliver verification suites/tests for ASICs, leveraging front-end simulators like VCS/NC and driving faster tape-out through coverage analysis and gate-level simulation sign-off.
Collaborate with logic designers for bug resolution and software developers for bring-up support, while also enhancing verification infrastructure through scripting (Perl, Python, shell).
Proficient in ASIC verification with SystemVerilog and UVM methodology.
Experience with constrained-random verification and scripting in Perl/Tcl preferred.
Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) is mandatory.
Onsite work at HPE office location is required.
Strong background in architecting and executing ASIC verification environments with emphasis on feature-rich and complex systems.
Experienced in using front-end simulators (VCS/NC) for coverage-driven verification and gate-level simulation sign-off.
Comfortable working closely with multi-disciplinary teams including logic designers and software developers in an agile environment for rapid issue resolution and product bring-up.