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Tier-1 brand and metro location increase competition, though role's niche verification skills limit applicant pool.
Role requires specific IP verification, SystemVerilog and digital design expertise, limiting cross-industry portability.
Mandatory 6+ years plus strict SystemVerilog/UVM and tool requirements create high shortlisting strictness.
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Lead IP-level verification efforts for hardware security components with accountability for testbench architecture, development, and debugging.
Ensure functional correctness and coverage of security-related IPs including cryptography, PRNG, and RSA algorithms.
Collaborate across teams to integrate verification methodologies and maintain high standards using UVM and SystemVerilog
6+ years of experience specifically in IP-level verification.
Proficiency in SystemVerilog and UVM including developing testbenches from scratch.
Strong understanding of digital design fundamentals, Verilog, and experience with VCS debugging tools.
Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, or related field with minimum 3 years hardware experience (higher degrees reduce this requirement accordingly)
Experienced in verification of security-related IPs such as cryptography and recognized algorithms like RSA or PRNG.
Familiar with bus protocols AHB, AXI, APB and functional/code coverage methodologies.
Hands-on operating style with deep knowledge of UVM testbench architecture and debugging complex designs using VCS tools