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Tier-1 employer, metro location and mid-level experience increase competition, but niche SMMU/UVM skills moderate density.
Highly specialized SoC verification skills and silicon debug focus limit cross-industry transferability.
Explicit years requirement and mandatory UVM/SystemVerilog and ARM protocol expertise create strict shortlisting filters.
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Own and maintain the design verification (DV) test bench and verification collateral for the System Memory Management Unit (SMMU) IP in next-generation SoCs.
Develop and execute test plans and cases ensuring functional and code coverage closure including collaborating with architects, design, and emulation teams for debugging and improvements.
Debug regression failures, root cause post-silicon issues, and develop/deploy validation tools and scripts to enhance verification efficiency.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years hardware engineering or related experience; or Master's with 3+ years; or PhD with 2+ years.
Expertise in UVM and System Verilog coding techniques mandatory.
Strong knowledge of ARM bus protocols (AXI, AHB, APB, CHI), virtual memory concepts, and SoC system architecture required.
Experience with post-silicon bring-up and HW-SW debugging, plus familiarity with silicon debug toolchains is a plus but not mandatory.
Proven track record owning complex IP design verification environments, especially for memory management or ARM-based SoCs.
Ability to interface effectively with cross-functional teams including system architects, design and emulation to drive issue resolution and verification completeness.
Experienced in developing advanced verification components (monitors, scoreboards, sequencers) using SystemVerilog/UVM and scripting for improved bug detection.