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Tier-1 brand and metro location increase competition, but niche hardware verification skills limit candidate pool.
Highly specialized ASIC/SoC verification skills and protocol expertise limit cross-industry transferability.
Specific SystemVerilog/UVM, protocol expertise, scripting skills and degree-plus experience create strict shortlisting filters.
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Develop and maintain UVM-based verification environments for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification tasks including functional coverage, assertion-based verification, and regression testing to ensure design correctness and coverage closure.
Collaborate with RTL designers, architects, and validation teams; contribute to verification methodology improvements and mentor junior engineers.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 4+ years hardware engineering experience; OR Master's degree with 3+ years experience; OR PhD with 2+ years experience.
Strong proficiency in System Verilog, UVM, verification methodologies, and scripting (Perl/Python/Tcl).
Deep understanding of PCIe Gen3 to Gen6, CXL 1.1 to 3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
Experience using third-party VIPs (Synopsys, Mentor) and expertise in assertion-based and coverage-driven verification.
Experienced verification engineer with 8–12+ years ASIC/Subsystem/SoC verification experience focused on high-speed interconnect protocols.
Demonstrated ability to lead verification closure efforts through coverage convergence and work closely with design and architecture teams.
Strong technical expertise in verification environments, scripting for automation, and mentoring junior engineers to advance verification methodologies.